1. Field of the Invention
The invention pertains to the field of display systems, and more particularly to a PC platform display system simulating a long persistence phosphor display.
2. Description of the Prior Art
There is a need to emulate a long persistence phosphor to improve digital radar displays. The realization of this improvement presents several problems:
Efficient processing of data during scan conversion requires the data to be in a 4 to 8 bits per pixel and a 1024 by 1024 pixel bitmap format, while the display format must be in a 32 bit per pixel true color. Present host computers are not capable of converting a 1024 by 1024 bitmap to a 32 bit true color at a fast enough rate for a radar display.
The scan conversion requires read-modify-write cycles to memory at a very high rate that is not practicable over a PCI bus due to the high latency times on the data reads.
To make the phosphor decay process appear visually over the entire radar display area, the changing data must be updated to the display at a fast rate. The computer is not capable of transporting the bitmap data from the scan converter to the graphics board at the required data rate without placing an excessive burden on the CPU.
Previous radar displays with fast updates were custom designed to accomplish this task. They used dual ported video memory that allowed the scan converter to be working in the same memory that is being displayed on the screen by the graphics hardware. The synergy of scan converter memory and display memory was very efficient, and capable of emulating the phosphor decay, but not possible on the open architecture PC platforms now required.
Another system of the prior art utilized a hardware scan converter in a PC platform for radar overlay which generated a bitmap in local memory that was incrementally transferred to a display memory by a Direct Memory Access process. This scan converter solution is also not capable of emulating the phosphor decay now required.